IBM three-dimensional – IBM says its fingernail-sized prototype chip—10mm by 15mm—reaches almost 100 billion transistors using a three-dimensional technique that links two silicon layers without overheating. The company claims 70% higher energy efficiency and 50% higher performance v
A chip the size of a fingernail has pushed the industry to a new edge: IBM’s prototype packs almost 100 billion transistors, with the company calling it a record density made possible by a three-dimensional manufacturing approach.
The prototype measures 10 millimetres by 15 millimetres. IBM says it could deliver 70 per cent higher energy efficiency and 50 per cent higher performance than current leading chips. It also puts a timetable on ambition: the technology would be in commercial devices within 10 years.
For decades, chip progress has been described through the size of individual transistors in nanometres—10 nanometres, 5 nanometres, and so on. But IBM’s Huiming Bu argues that the naming has stopped matching physical reality. Size labels, he says, have become marketing terms, decoupled from any real measurement of transistor dimensions.
IBM’s “0.7 nanometre” claim is part of that shift. Bu doesn’t frame the breakthrough as smaller transistor parts in the usual sense. The innovation. he says. is the ability to “stick together two layers of silicon chips” in a way that produces the electrical connections between layers. avoids overheating. and can be mass produced. “Our whole industry has been scaling transistors in the X-axis dimension and the Y-axis dimension for all the 60-plus years [of chip manufacturing]. ” Bu says. “It’s the first time we’ll enable transistor scaling in the Z direction.”.
IBM did not provide precise details on the dimensions of components in this new technology. But the information it released points to a process described as essentially two layers of the first working 2-nanometre chip that IBM announced in 2021. That earlier technology is said to be manufactured by many of the world’s leading chip foundries. and it is expected to make its way into the next Apple iPhone.
Behind the scenes, chip development is less a solo race than a long collaborative effort. Because designing and producing new chips is both complex and expensive. companies follow roadmaps that spell out what technologies must be created and brought to market. and by when. That process is orchestrated by the not-for-profit Interuniversity Microelectronics Centre, which does much of the research and development. IBM’s 0.7-nanometre technology. while not yet commercially tested. is described as an expected step in global chip-making—one that will likely be followed by other makers.
Even so, the push toward ever finer scales is colliding with fundamental limits. Bu says the technology increasingly has to push against the laws of physics to fight unwanted quantum effects. current leakage. and other problems that emerge at such minuscule scales. Parts of the latest chips are just 15 silicon atoms thick.
That’s where skepticism enters. Owen Guy at Swansea University in the UK says other chip makers are making claims about similarly high transistor density that don’t match IBM’s description of true 3D design. He argues that some competitors use multiple layers of silicon separated by thick layers of substrate. which he says doesn’t allow the kind of connections IBM claims—and that it can also create cooling problems. “There’s a lot of smoke and mirrors about this stuff now.”.
Guy also questions what users would actually feel from such shrinking. Chip components are now so small. he says. that shrinking transistor size—even when it involves billions of them—won’t make everyday devices like laptops or smartphones smaller in practice. In his view, the real payoff is not size. It’s energy efficiency and cooling. which can translate into better battery life for mobile devices and lower energy use in data centres.
The route from prototype to mass production may be the hardest part. Chips are manufactured in batches of hundreds on a single 300-millimetre silicon wafer containing trillions of transistors. then cut into individual parts. Thousands of operations are performed on each wafer. laying down layers of circuit. insulation. and chemicals with thicknesses of just a few nanometres. Adding an untested new feature like IBM’s second layer. Guy notes through the manufacturing reality IBM must face. won’t be simple.
Some industry plans already point beyond IBM’s “0.7-nanometre” milestone. A smaller “0.2-nanometre” technology is mentioned, at which point parts of a circuit could be a single atom wide. Guy says the ultimate limit is “one electron and one atom.” He adds that it’s probably around the 2050 mark when quantum technologies will be needed to make the next big leap.
For now, IBM’s prototype is a statement of what’s possible: almost 100 billion transistors on a chip measuring just 10mm by 15mm, enabled not by only going smaller, but by going layered—pushing the manufacturing process into a third dimension.
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