XCENA raises $135M to move AI workloads near DRAM

XCENA raises – XCENA, a four-year-old chip startup with offices in South Korea and the U.S., raised $135 million in a Series B at a $570 million valuation—betting that AI’s biggest bottleneck is memory rather than raw compute. Its prototype MX1 connects to CPUs via CXL to pr

Every time you ask ChatGPT a question. your request triggers something like a data relay race—information leaves memory. passes through a CPU for preprocessing. travels to a GPU for heavy computation. then makes its way back again. And that same journey repeats for every single word the AI generates.

XCENA is trying to break that loop at the source. The four-year-old startup. with offices in South Korea and the U.S. designed a chip that places compute capabilities much closer to DRAM. the fast short-term memory chips that store data a processor is actively using. The promise is straightforward: routine data operations handled near memory, without costly round trips between CPUs, GPUs, and memory.

For investors. the bet is simple enough to sound profitable: if this approach works at scale. AI infrastructure costs could drop in a very visible way—especially when the traffic through those expensive chips is repeated for every request. That enthusiasm showed up in the company’s latest funding round. XCENA raised $135 million in a Series B at a valuation of $570 million, bringing its total raised to $185 million.

The company’s thesis is rooted in a mismatch it says has endured for too long. XCENA CEO Jin Kim—who co-founded the startup in 2022 with CTO Dohun Kim and CPO Harry Juhyun Kim—argued that while CPUs and GPUs have improved over decades. memory hasn’t kept pace. Kim. a veteran of Samsung and SK Hynix along with the other co-founders. also pointed to what he sees as a signal in markets: the recent rise in memory prices and related stocks. which he said points to a broader shift in AI infrastructure toward memory-centric architectures.

The backdrop to that claim is stark for the memory industry. This month, the three companies that dominate the global memory chip market—Samsung, SK Hynix, and Micron—each crossed a trillion-dollar valuation for the first time.

XCENA is betting its business on a line that frames the entire company: “inference isn’t just a compute problem; it’s increasingly a memory scaling problem,” said Kim.

Its chip. the MX1. connects to the CPU through CXL (Compute Express Link)—described as a dedicated express lane between the processor and memory. The key idea is that MX1 processes data before it ever needs to leave the memory module. bringing compute to the data instead of forcing the data to travel.

XCENA claims the potential payoff could be dramatic. What used to require 10 servers, the company says, could potentially run on just one.

Kim drew a clear boundary between where GPUs shine and where the bottlenecks still sit. “While GPUs excel at matrix multiplication—the heavy math behind AI model training—much of the surrounding data orchestration. including preprocessing. KV cache management [the system that stores prior conversation context so a model doesn’t have to reprocess it]. and data caching. still runs on CPUs. ” Kim said. “Our chip handles those tasks directly within the memory module itself.”.

Demand for memory solutions has surged since the second half of last year, and XCENA believes the timing is working in its favor. Conversations with several global memory vendors are in early stages, though Kim declined to name them.

The company is aiming its pitch at hyperscalers—big buyers who spend tens of billions a year on AI infrastructure—where even small improvements in memory efficiency can translate into hundreds of millions in savings.

Still, the MX1 is not shipping today. The chip is described as a prototype, with mass production chips scheduled to roll off Samsung’s foundry lines by the end of 2026. XCENA expects to generate revenue starting in 2027.

Competition is already circling the larger AI silicon picture. While neural processing unit (NPU) makers compete to challenge Nvidia for training workloads, XCENA is targeting what sits underneath much of that race: the memory-intensive layer.

Its closest rivals include Astera Labs and Marvell, both Nasdaq-listed companies working on next-generation memory connectivity. Kim said Marvell is a large, established player already working in the same space. He argued the differentiator comes down to intellectual property: “We have thousands of cores,” Kim said. Based on public specs, he said Marvell’s approach relies on a handful of general-purpose cores by comparison.

XCENA’s design uses RISC-V, an open-source chip design blueprint, and aims to optimize for data processing. Kim described each core as deliberately small and efficient. Beyond the cores themselves. XCENA designs its own internal memory hierarchy. interconnect bus. and DRAM controller—an unusual level of vertical integration that most chip companies. including larger rivals. typically outsource.

Funding also reflects how seriously investors are taking the memory angle. The Series B was co-led by Seoul-based VC firms Altinum and IMM Investment. along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. XCENA has more than 90 staff across offices in Pangyo, a tech hub outside Seoul, and in Sunnyvale. The company is also in conversations with international investors about additional funding.

If XCENA’s prototype timing and scalability live up to the vision, it could reshape where the biggest pressure points land in AI infrastructure. In a world where every generated token triggers another pass through the same expensive path, the hope is that the next pass won’t have to travel so far.

XCENA MX1 DRAM CXL AI infrastructure memory-centric architecture Series B hyperscalers KV cache RISC-V Samsung foundry Astera Labs Marvell